1. Technical Field
The present disclosure relates to fractional frequency divider circuits. More specifically, the present disclosure relates to a fractional frequency divider circuit used in a clock generation circuit that generates a clock frequency represented by at fractional ratio relative to a source oscillation clock by using a digital frequency divider.
2. Related Art
In recent years, High-Definition Multimedia Interface (HDMI) has been known as the standard specification for the digital video and audio input/output interface, which is established mainly for the home electric appliances and audio visual (AV) appliances. The HDMI connects the source device (transmission (output) appliance) and a sink device (reception (input) appliance). The sink device receives parameters for reproducing the audio clock from the source device via the HDMI. That is, the parameters include a value (N), which is used as a frequency division ratio by the frequency divider circuit and a cycle time stamp value (CTS) as a value representing the cycle speed of the audio clock based on the video clock. A combination of CTS and N together with the Transition Minimized Differential Signaling (TMDS) clock represents the frequency division ratio of the audio clock. The sink device carries out the fractional frequency division using these parameters to reproduce the audio clock from the TMDS clock. Exemplary configurations of the fractional frequency divider circuit are described in Patent Literatures below.    [Patent Literature 1] JP-A-S54-025658    [Patent Literature 2] JP-A-H2-096429    [Patent Literature 3] JP-A-H2-271717    [Patent Literature 4] JP-A-H8-242165    [Patent Literature 5] JP-A-H11-098007    [Patent Literature 6] JP-A-2006-174197    [Patent Literature 7] JP-A-H3-155219    [Patent Literature 8] JP-A-H4-083425    [Patent Literature 9] JP-A-2009-267651